Design-in reliability for over drive applications in advanced technology

Author

Ahn, Jae-Gyung ; Yeh, Ping-Chin ; Sowards, Jane ; Lo, Nick ; Chang, Jonathan

Author_Institution

Si-Tech Group, Xilinx, Inc., San Jose, CA, USA

fYear

2010

fDate

17-21 Oct. 2010

Firstpage

157

Lastpage

160

Abstract

We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, V_{g_max}, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.

Keywords

MOSFET; hot carriers; semiconductor device models; semiconductor device reliability; BTI; FEOL reliability checking; HCI degradation analysis; HSPICE MOSRA simulation; MOSFET device; NCHC; SPICE transient simulation; advanced technology; bias temperature instability; circuit performance; design in reliability; end-of-lifetime; gate bias; hot carrier injection; over drive application; Circuit optimization; Degradation; Human computer interaction; Integrated circuit modeling; Logic gates; Reliability; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Conference_Location

Stanford Sierra, CA

ISSN

1930-8841

Print_ISBN

978-1-4244-8521-5

Type

conf

DOI

10.1109/IIRW.2010.5706513

Filename

5706513