• DocumentCode
    2412452
  • Title

    PLFire: a visualization tool for asynchronous phased logic designs

  • Author

    Fazel, K. ; Thornton, M.A. ; Reese, R.B.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
  • fYear
    2003
  • fDate
    2003
  • Firstpage
    1096
  • Lastpage
    1097
  • Abstract
    We present a visualization tool called PLFire, which allows a user to observe the behavior of a Phased Logic (PL) circuit. Phased logic is a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock. One advantage of self-timed circuits is that throughput is based on average propagation delays and not worst-case delay. By being able to visualize the operation of a PL circuit, including the token flow, a designer gets a better understanding of what features of a design have the greatest impact on performance.
  • Keywords
    asynchronous circuits; asynchronous sequential logic; data visualisation; delays; logic CAD; PLFire; asynchronous phased logic designs; average propagation delays; phased logic circuit; self-timed circuitry; throughput; token flow; visualization tool; Circuit synthesis; Clocks; Data visualization; Design methodology; Field programmable gate arrays; Logic circuits; Logic design; Propagation delay; Signal design; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2003
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1870-2
  • Type

    conf

  • DOI
    10.1109/DATE.2003.1253751
  • Filename
    1253751