LIT - an automatic layout generation tool for trapezoidal association of transistors for basic analog building blocks

This paper describes a methodology for analog layout synthesis based on the automatic generation of an equivalent composite transistor with the same DC current characteristics of the transistors in the electrical schematic. The tool serves a dual purpose: i) the layout synthesis of analog blocks over a digital sea-of-gates prediffused array, and ii) the generation of custom associations of transistors for matched common-source input pairs and current mirrors. The LIT tool generates the layout in a line-matrix, sea-of-gates with gate isolation style of several blocks: the trapezoidal-like composite transistors and of matched transistor pairs. In addition, the tools provides an environment for manual analog cells placement and automatic routing. These features drastically reduce the design time, reduce costs and include matching properties.