Title :
Micro-network for SoC: implementation of a 32-port SPIN network
Author :
Andriahantenaina, Adrijean ; Greiner, Alain
Author_Institution :
LIP6 Lab., Univ. Pierre et Marie Curie, Paris, France
Abstract :
We present a physical implementation of a 32-ports SPIN (scalable programmable integrated network) micro-network. For a 0.13 μm CMOS process, the total area is 4.6 mm2, for a cumulated bandwidth of about 100 Gbits/s. In a 6 metal process, all the routing wires can be routed on top of the switching components. The SPIN32 macro-cell will be fabricated by ST Microelectronics, but this macrocell uses a symbolic layout, and can be manufactured with any CMOS process including 6 metal layers.
Keywords :
CMOS digital integrated circuits; integrated circuit design; integrated circuit interconnections; multistage interconnection networks; packet switching; system-on-chip; telecommunication network routing; 0.13 micron; 100 Gbit/s; CMOS; SPIN network; SPIN32 macro-cell; SoC micro-network; fat tree topology; micro-network cumulated bandwidth; multistage network; packet switching; scalable programmable integrated network; symbolic layout; wire routing; wormhole type routing; Automatic control; Bandwidth; CMOS process; Coprocessors; Macrocell networks; Microelectronics; Network topology; Routing; Telecommunication network topology; Wires;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253766
