DocumentCode :
2412913
Title :
Decomposition of extended finite state machine for low power design
Author :
Lee, Ming Hung ; Hwang, Ting Ting ; Huang, Shi-Yu
Author_Institution :
Dept. of Comput. Sci., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
fYear :
2003
fDate :
2003
Firstpage :
1152
Lastpage :
1153
Abstract :
Power reduction can be achieved by turning off portions of circuits that are idle. Unlike previous work, which focused only on either controller or data-path, we propose a decomposition technique that takes both controller and data-path into consideration where, in the former, the state probability of an FSM provides the execution frequency of operations in that state. And, in the latter, operations performed in states provide the information of resource requirements which can be used to determine the resource sharing among states. The goal is to synthesize circuits such that the submachine with small area (data-path and controller) will be turned on most of the time (high state probability) and all other parts are turned off. Our experimental results show that on the average, 101% area reduction and 24 % power reduction can be achieved as compared with designs without decomposition.
Keywords :
data flow graphs; finite state machines; logic design; low-power electronics; EFSM decomposition; FSM controller; FSM data-path; FSM state probability; area reduction; data flow graph; extended finite state machine; idle circuit turn off; low power design; power reduction; resource sharing; Automata;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253777
Filename :
1253777
Link To Document :
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