Title :
A high-level WSI yield simulation system
Author :
Harden, J.C. ; Wang, J.J. ; Tebbs, B.W.
Author_Institution :
Dept. of Electr. Eng., Mississippi State Univ., MI, USA
Abstract :
This system generates a description of a cellular wafer-scale design including the cell locations and the interconnections between the cells. The functional interdependency of each cell is also defined in terms of necessary lists. From this description, a database that contains the circuit descriptions is created. The system then determines (according to statistical algorithms) which circuit cells are defective and reports the effective wafer-scale yield of the circuit
Keywords :
VLSI; cellular arrays; cell locations; cellular wafer-scale design; circuit descriptions; database; effective wafer-scale yield; functional interdependency; high-level; interconnections; statistical algorithms; yield simulation system; Analytical models; Commercialization; Computational modeling; Computer science; Databases; Design optimization; Fabrication; Integrated circuit interconnections; Predictive models; Semiconductor device modeling;
Conference_Titel :
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9901-9
DOI :
10.1109/WAFER.1989.47554
