Title :
Consequences of RAM bitline twisting for test coverage
Author :
Schanstra, Ivo ; Van de Goor, Ad J.
Author_Institution :
Infineon Technol. AG, Munich, Germany
Abstract :
In order to reduce coupling effects between bitlines in static or dynamic RAMs bitline twisting can be used in the design. For testing, however, this has consequences for the to-be-used data backgrounds. A generic twisting scheme is introduced and the involved fault models are identified.
Keywords :
DRAM chips; SRAM chips; fault diagnosis; integrated circuit testing; RAM bitline twisting; coupling effects; dynamic RAMs; fault models; generic twisting scheme; static RAMs; test coverage; to-be-used data backgrounds; DRAM chips; Design engineering; Europe; Fault diagnosis; Information technology; Logic; Random access memory; Read-write memory; Systems engineering and theory; Testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253788
