PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

Author

Wu, W. ; Li, X. ; Gildenblat, G. ; Workman, G. ; Veeraraghavan, S. ; McAndrew, C. ; van Langevelde, R. ; Smit, G.D.J. ; Scholten, A.J. ; Klaassen, D.B.M. ; Watts, J.

Author_Institution

Arizona State Univ., Tempe

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

41

Lastpage

48

Abstract

This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.

Keywords

MOSFET; semiconductor device models; silicon-on-insulator; PSP-SOI; SOI devices; compact model; floating body simulation; industry standard bulk MOSFET model; nonlinear body resistance; parasitic bipolar model; partially depleted SOI MOSFET; partially depleted SOI modeling; self heating; surface potential; CMOS technology; Capacitance; Circuits; Immune system; MOSFETs; Manufacturing processes; Semiconductor device modeling; Surface resistance; Threshold voltage; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405678

Filename

4405678