DocumentCode
2413336
Title
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections
Author
Wu, Jian-Yi ; Subramoniam, Raj ; Zhang, Zhenyong ; Djabbari, Ali ; Holloway, Peter ; Maloberti, Franco ; Yousefi, Masood ; Aslan, Mehmet ; Hong, Hua ; Bahai, Ahmad
Author_Institution
Nat. Semicond., Santa Clara
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
77
Lastpage
80
Abstract
A novel second order sigma delta modulator (SDM) with 5-bit quantizer has been proposed with simplified DAC arrays, high-order truncation noise shaping for increased tolerance to analog imperfections, and extended dynamic range for a maximum input signal swing of up to -0.45 dBFS. With truncation filter and pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design was fabricated in 0.18mu dual gate oxide (DGO) process. A SNDR (signal-to-noise-and-distortion ratio) of 98.4 dB and a SNR (signal-to-noise ratio) of 108-dB were measured for a 31.25-KHz signal bandwidth at 8-MHz sampling frequency with a power consumption of about 14.7 mW.
Keywords
circuit feedback; sigma-delta modulation; DSP; analog imperfections; bandwidth 31.25 kHz; dual gate oxide process; extended dynamic range; frequency 8 MHz; high-order truncation noise shaping; multi-bit sigma delta ADC; noise figure 108 dB; noise figure 98.4 dB; power 14.7 mW; pseudo SDM; reduced feedback levels; second order sigma delta modulator; signal-to-noise-and-distortion ratio; simplified DAC arrays; truncation filter; Delta modulation; Delta-sigma modulation; Digital signal processing; Dynamic range; Feedback; Filters; Frequency measurement; Noise shaping; Power measurement; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405685
Filename
4405685
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