Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

Author

Bernard, E. ; Ernst, T. ; Guillaumot, B. ; Vulliet, N. ; Barral, V. ; Maffini-Alvaro, V. ; Andrieu, F. ; Vizioz, C. ; Campidelli, Y. ; Gautier, P. ; Hartmann, J.M. ; Kies, R. ; Delaye, V. ; Aussenac, F. ; Poiroux, T. ; Coronel, P. ; Souifi, A. ; Skotnicki

Author_Institution

Minatec, CEA/LETI, Grenoble

fYear

2008

fDate

17-19 June 2008

Firstpage

16

Lastpage

17

Abstract

For the first time, ultra low I_OFF (16.5 pA/mum) and high I_ONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best I_ON/I_OFF ratios ever reported: 1.4 times 10⁸ (0.8 times 10⁸) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Keywords

MOSFET; high-k dielectric thin films; low-power electronics; silicon-on-insulator; 3D MCFET features; 3D multichannel CMOSFET; SOI; electrostatic behavior; integration process; low standby power; metal/high-K gate stack; saturation regime; transport properties; CMOSFETs; Degradation; Delay; Electrical resistance measurement; High K dielectric materials; High-K gate dielectrics; Performance analysis; Scattering; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588546

Filename

4588546