Title :
CAD Techniques for Power Optimization in Virtex-5 FPGAs
Author :
Gupta, Subodh ; Anderson, Jason ; Farragher, Linda ; Wang, Qiang
Author_Institution :
Xilinx Inc., San Jose
Abstract :
We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.
Keywords :
circuit optimisation; field programmable gate arrays; logic CAD; network routing; power consumption; CAD techniques; Virtex-5 FPGA; board-level power measurements; dynamic power dissipation; dynamic power reduction; industrial designs; post-routing transformation; power optimization; power-aware placement; Capacitance; Design automation; Design optimization; Energy consumption; Fabrics; Field programmable gate arrays; Integrated circuit interconnections; Power dissipation; Routing; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405687
