DocumentCode
2413487
Title
Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models
Author
Zhao, Jun ; Meyer, Fred J. ; Lombardi, Fabrizio
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear
2000
fDate
2000
Firstpage
14
Lastpage
19
Abstract
This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults)
Keywords
fault diagnosis; integrated circuit interconnections; integrated memory circuits; bus-connected multi RAM systems; general fault model; interconnect faults; multiple RAM chips; restricted fault model; Computer science; Electrical fault detection; Fault detection; Fault diagnosis; Joining processes; Random access memory; Read-write memory; System testing; Virtual manufacturing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on
Conference_Location
San Jose, CA
ISSN
1087-4852
Print_ISBN
0-7695-0689-5
Type
conf
DOI
10.1109/MTDT.2000.868610
Filename
868610
Link To Document