DocumentCode
2413564
Title
Testing SerDes beyond 4 Gbps - changing priorities
Author
Sunter, Stephen ; Roy, Aubin
Author_Institution
LogicVision, Ottawa
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
135
Lastpage
138
Abstract
After briefly reviewing conventional jitter and jitter tolerance tests for SerDes, this paper shows that ISI is a dominant source of bit errors above 4 Gbps, and is inadequately tested. We demonstrate the correlation between ISI and transition-density dependent delay (TDDD) at 3.1 Gbps, and provide detailed 6.25 Gbps silicon results for an undersampling digital BIST that can measure jitter, TDDD, and other parameters at production speeds with picosecond resolution.
Keywords
error statistics; intersymbol interference; jitter; SerDes; bit error rate; bit errors source; bit rate 4 Gbit/s; jitter tolerance tests; serializer-deserializer system; transition-density dependent delay; Bit error rate; Circuit testing; Delay; Frequency measurement; Intersymbol interference; Jitter; Manufacturing processes; Phase measurement; Production; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-0786-6
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405698
Filename
4405698
Link To Document