Title :
Tutorial: synchronous dynamic memory test construction-a field approach
Author_Institution :
White Oak Semicond., Sandston, VA, USA
Abstract :
This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification
Keywords :
integrated circuit testing; integrated memory circuits; basic pattern; march test; memory tests; synchronous dynamic memory test; test flows; test sequence; Analog circuits; Capacitors; Circuit testing; Logic circuits; Logic testing; SDRAM; Semiconductor device testing; Timing; Tutorial; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0689-5
DOI :
10.1109/MTDT.2000.868616
