Title :
On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks
Author :
Jenkins, K.A. ; Shepard, K.L. ; Xu, Z.
Abstract :
A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.
Keywords :
jitter; logic circuits; logic design; clock distribution network; clock skew measurement; latch; onchip circuit; period jitter; voltage-controlled delay element; Circuit testing; Clocks; Delay effects; Frequency measurement; Integrated circuit measurements; Jitter; Latches; Network-on-a-chip; Semiconductor device measurement; Time measurement; Jitter; built-in self test; clock distribution; clock skew; on-chip measurement; period jitter;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405703
