DocumentCode
2413717
Title
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter
Author
Ichiyama, Kiyotaka ; Ishida, Masahiro ; Yamaguchi, Takahiro J. ; Soma, Mani
Author_Institution
Advantest Lab. Ltd., Sendai
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
161
Lastpage
164
Abstract
A new design for a mismatch-tolerant on-chip data jitter measurement circuit in 0.11-mum CMOS is experimentally verified in this paper. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The circuit´s tolerance to data-rate changes is verified using 2.5 Gbps and 2.98 Gbps PRBS signals. The jitter gain of the prototype circuit is also shown to be less sensitive to variations in the supply voltage.
Keywords
CMOS integrated circuits; convertors; integrated circuit testing; jitter; CMOS; complementary metal-oxide-semiconductor; data-to-clock converter; integrator; jitter gain; mismatch-tolerant circuit; on-chip data jitter measurement circuit; pulse generator; size 0.11 mum; CMOS logic circuits; Capacitors; Circuit testing; Clocks; Delay; Jitter; Logic design; Pulse generation; Pulse measurements; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405704
Filename
4405704
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