Optimizing memory bandwidth with ILP based memory exploration and assignment for low power embedded systems

In this paper, we describe a low power memory design procedure that optimizes memory bandwidth in VLSI sytems. We develop the procedures of loop transformation to optimize the memory cost for the required storage bandwidth. Next, we develop memory assignment based on ILP model that is derived from mapping graph (MG) such that we can find (i) the best memory configuration (minimum-area memory configuration if power is bound or minimum-power memory configuration if area is bound) and (ii) the power/area efficient array assignment to given memory library (the number of memory banks, the number of ports, and the total memory size)