Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiO_x interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91 nm directly on SiGe with leakage equivalent to bulk Si. High I_on (1.5times Si), and low subthreshold slope (73 mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.