Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Author

Aikawa, H. ; Morifuji, E. ; Sanuki, T. ; Sawada, T. ; Kyoh, S. ; Sakata, A. ; Ohta, M. ; Yoshimura, H. ; Nakayama, T. ; Iwai, M. ; Matsuoka, F.

Author_Institution

Adv. Logic Technol. Dept. Syst. LSI Div., Toshiba Corp. Semicond. Co., Yokohama

fYear

2008

fDate

17-19 June 2008

Firstpage

90

Lastpage

91

Abstract

Gate density is ultimately increased to 2100 kGates/mm² by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit layout; integrated circuit modelling; nanotechnology; CMOS; MOSFET; size 45 nm; stress enhancement technique; variability aware modeling; Circuit simulation; DSL; Libraries; Lithography; MOSFET circuits; SPICE; Semiconductor device modeling; Shape; Space technology; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588574

Filename

4588574