Title :
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability
Author :
Badrudduza, Sayeed A. ; Clark, Lawrence T.
Author_Institution :
Arizona State Univ., Tempe
Abstract :
Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 mum CMOS process technology. The cells are 11% larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.
Keywords :
CMOS digital integrated circuits; CMOS memory circuits; SRAM chips; CMOS process technology; SRAM cell; complementary metal-oxide-semiconductor; memory test circuit; read stability; size 0.13 mum; static noise margin; static random access memory; transistor cell; transistor leakage; CMOS process; CMOS technology; Circuit noise; Circuit stability; Circuit testing; Low voltage; Power measurement; Random access memory; SRAM chips; Velocity measurement;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405719
