Dynamic Data Stability in Low-power SRAM Design

SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13 mum CMOS consumes 702 muW at 100 MHz during write operation and offers a 27 pA/Cell leakage current.