DocumentCode :
2414128
Title :
Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application
Author :
Koo, June-Mo ; Yoon, Tae-Eung ; Lee, Taehee ; Byun, Sungjae ; Jin, Young-Gu ; Kim, Wonjoo ; Kim, Sukpil ; Park, Jongbong ; Cho, Junseok ; Choe, Jeong-Dong ; Lee, Choong-Ho ; Lee, Jong Jin ; Han, Je-Woo ; Kang, Yunseung ; Park, Sangjun ; Kwon, Byoungho ; J
Author_Institution :
Samsung Adv. Inst. of Technol., Yongin
fYear :
2008
fDate :
17-19 June 2008
Firstpage :
120
Lastpage :
121
Abstract :
Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND flash array cells with TANOS (TaN/Al2O3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND flash application.
Keywords :
MOSFET; NAND circuits; flash memories; nitrogen compounds; silicon compounds; tantalum compounds; TANOS charge trap structure; TaN-Al2O3-SiN-SiOx-Si; erase properties; flash memories; ion implantation; isolation material; paired FinFET multibit scheme; program properties; vertical structure NAND flash array integration; word line patterning; Aluminum oxide; Etching; FinFETs; Flash memory; Ion implantation; Silicon compounds; Testing; Threshold voltage; Vehicles; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2008 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1802-2
Electronic_ISBN :
978-1-4244-1803-9
Type :
conf
DOI :
10.1109/VLSIT.2008.4588586
Filename :
4588586
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2414128
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