Title :
On a low power distributed arithmetic design with GA-based optimization approach
Author :
Chen, Hun-Chen ; Yen, Jui-Cheng ; Fan, Kuo-Tai ; Lin, Chih-Yung ; Huang, Po-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. United Univ., Miaoli, Taiwan
Abstract :
In this paper, based on genetic algorithm (GA) an optimization approach is proposed to the arrangement of memory content in group distributed arithmetic (GDA) architecture with low power consumption. According to the information of data such as a kind of image sequence, we take one in the sequence to find an arrangement of memory content to have the near optimal transition activity on the data bus of memory in GDA design. With more than two generations of calculation by genetic algorithm, the arrangement of memory content facilitates low power consumption for the GDA design. The simulation result shows the hamming distance on the memory output of GDA design is reduced around 15.6%. And the power consumption can be reduced more than 6.4% on the verification of GDA hardware.
Keywords :
digital arithmetic; genetic algorithms; logic design; low-power electronics; data bus; genetic algorithm; group distributed arithmetic architecture; hamming distance; image sequence; low power consumption; memory; Algorithm design and analysis; Arithmetic; Design optimization; Energy consumption; Genetic algorithms; Hamming distance; Hardware; Image sequences; Mathematical model; Power generation;
Conference_Titel :
Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-2975-2
Electronic_ISBN :
978-1-4244-2976-9
DOI :
10.1109/ISCE.2009.5156884