Title :
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES
Author :
Maangat, Simar ; Nguyen, Toan ; Wong, Wilson ; Shumarayev, Sergey ; Tran, Tina ; Hoang, Tim ; Cliff, Richard
Author_Institution :
Altera Corp., San Jose
Abstract :
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.
Keywords :
CMOS logic circuits; error statistics; intersymbol interference; programmable logic devices; synchronisation; transceivers; PLD integrated SERDES; TSMC CMOS logic process; bit error rate; clock data recovery circuit; duty cycle distortion; inter symbol interference; receiver offset cancellation; size 90 nm; soft intellectual property core; transceiver channel; voltage offsets; wide-range transceiver; Bit error rate; CMOS logic circuits; CMOS process; Clocks; Degradation; Distortion measurement; Logic design; Transceivers; Transmitters; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405729
