Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC

Author

Von Kaenel, Vincent ; Takayanagi, Toshinari

Author_Institution

Freedom Circle, Santa Clara

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

269

Lastpage

272

Abstract

Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.

Keywords

cryptography; multiprocessing systems; random number generation; system-on-chip; CMOS process; bit stream randomness; chaotic true random number generator; complementary metal-oxide-semiconductor; cryptographic application; data dependent noise; dual CPU SoC; dual true random number generator; random bit rate; size 65 nm; system-on-chip; thermal noise; CMOS process; Chaos; Chaotic communication; Circuit noise; Cryptography; Noise generators; Oscillators; Random number generation; Signal to noise ratio; White noise; Chaos; Random number generation; Random number generator; True random number generator; White noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405730

Filename

4405730