DocumentCode
2414324
Title
Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications
Author
Bidal, G. ; Boeuf, F. ; Denorme, S. ; Loubet, N. ; Laviron, C. ; Leverd, F. ; Barnola, S. ; Salvetat, T. ; Cosnier, V. ; Martin, F. ; Grosjean, M. ; Perreau, P. ; Chanemougame, D. ; Haendler, S. ; Marin, M. ; Rafik, M. ; Fleury, D. ; Leyris, C. ; Clement,
Author_Institution
STMicroelectron., Crolles
fYear
2008
fDate
17-19 June 2008
Firstpage
146
Lastpage
147
Abstract
This work highlights the new bulk+ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to Tsi= 8 nm) and thin BOX (Tbox = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (Wdesign/Lgate= 90 nm/40 nm) at Vdd = 1.1 V and Ioff < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum2 are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.
Keywords
MOSFET; SRAM chips; hafnium; high-k dielectric thin films; low-power electronics; nanotechnology; titanium compounds; 6T-SRAM bit cells; Hf; TiN; TiN/Hf-based gate stack; fully depleted SON; fully depleted silicon on nothing channel; high-K dielectric; low power applications; nMOS; pMOS; planar bulk+ technology; silicon channel; single metal gate; Circuits; Costs; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; MOS devices; Parasitic capacitance; Random access memory; Silicon germanium; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2008 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-1802-2
Electronic_ISBN
978-1-4244-1803-9
Type
conf
DOI
10.1109/VLSIT.2008.4588596
Filename
4588596
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