Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique

Time-aligned correlated double sampling (CDS) technique, which overcomes the error accumulation problem found in the time-shifted CDS technique, is proposed. This technique allows low gain opamp based switched-capacitor operation to achieve the equivalent accuracy that is traditionally possible only in high gain opamp based switched-capacitor operation. This allows simple single stage opamps to be used, leading to low-power and high-speed performance. As a proof of concept, a prototype pipelined analog-to-digital converter (ADC) is fabricated in a 0.18 mum CMOS process. Measured results demonstrate 1.8V 10b 100 MS/s 50 mW ADC.