• DocumentCode
    2414550
  • Title

    An integrated system architecture for binary image understanding

  • Author

    Deb, Alak ; Ling, Nam

  • Author_Institution
    Synopsys, Inc., Mountain View, CA, USA
  • fYear
    1993
  • fDate
    15-17 Dec 1993
  • Firstpage
    446
  • Lastpage
    454
  • Abstract
    The authors take a holistic approach to developing a system level architecture for the problem of image capture and understanding in binary images. It includes a direct method of image capture that removes many of the I/O bottlenecks inherent in other systems. It also cooperates with an adaptive focusing mechanism in order to be able to provide quickly and efficiently a higher resolution image for a sub-area of the total scene whenever foveal attention is required, which would need considerable overhead in most systems thereby precluding real-time behavior. The architecture supports all the three levels of vision processing (low, intermediate, and high) for real time object recognition in binary images by providing parallel mesh connected simple processors (PEs) for low level processing as well as a hierarchy of successively powerful PEs providing a pyramidal type of structure for higher levels of processing. It is also shown that this can be efficiently implemented as a dense and regular single or multiple VLSI chips making possible direct mounting of the system inside a camera. On the processor (PE) level the authors have added enhancements over previous architectures that make it possible to form a fast and economical image understanding system for all three levels of processing for binary images. The main contribution has been the generally broad system level approach of active vision to the development of the architecture and the three enhancements to the PEs which include a switchbox mechanism for extending the local connectivity to establish communications between nonlocal neighbors, a hardware implementation of an artificial neural network that provides direct support for connectionist processing, and an embedded multilevel pyramid with successively powerful PEs. This is shown to fulfill the processing requirements for real-time binary image understanding applications
  • Keywords
    image processing; VLSI chips; active vision; adaptive focusing mechanism; artificial neural network; binary image understanding; camera; communications; connectionist processing; direct mounting; embedded multilevel pyramid; foveal attention; hardware implementation; holistic approach; image capture; integrated system architecture; local connectivity; nonlocal neighbors; parallel mesh connected simple processors; real time object recognition; sub-area; switchbox mechanism; system level architecture; total scene; vision processing; Cameras; Communication switching; Focusing; Image resolution; Layout; Neural network hardware; Object recognition; Power generation economics; Real time systems; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architectures for Machine Perception, 1993. Proceedings
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    0-8186-5420-1
  • Type

    conf

  • DOI
    10.1109/CAMP.1993.622502
  • Filename
    622502