• DocumentCode
    2414552
  • Title

    A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

  • Author

    Brownlee, Merrick ; Hanumolu, Pavan Kumar ; Moon, Un-Ku

  • Author_Institution
    Oregon State Univ., Corvallis
  • fYear
    2007
  • fDate
    16-19 Sept. 2007
  • Firstpage
    353
  • Lastpage
    356
  • Abstract
    A 3.2 Gbps CDR circuit employs an oversampling architecture to decouple the tradeoff between jitter generation and jitter tolerance. The test chip fabricated in a 0.13 mum CMOS process achieves a 30times increase in the jitter tolerance corner without increasing recovered clock jitter. Power consumption is 19.5 mW from a 1.4 V supply at 3.2 Gbps and die area is 0.081 mm2.
  • Keywords
    CMOS digital integrated circuits; clocks; integrated circuit testing; jitter; CMOS process; bit rate 3.2 Gbit/s; jitter generation; jitter tolerance; oversampling CDR; power 19.5 mW; power consumption; recovered clock jitter; size 0.13 mum; test chip; voltage 1.4 V; Bandwidth; Circuits; Clocks; Energy consumption; Flip-flops; Jitter; Phase detection; Phase frequency detector; Sampling methods; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-1623-3
  • Electronic_ISBN
    978-1-4244-1623-3
  • Type

    conf

  • DOI
    10.1109/CICC.2007.4405751
  • Filename
    4405751
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2414552