A 10-bit 40MS/s pipelined ADC with pre-charged switched operational amplifier

Author

Wei, Qi ; Yang, Huazhong

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

fYear

2009

fDate

25-28 May 2009

Firstpage

403

Lastpage

407

Abstract

This paper describes a 10-bit 40 MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82 mW. The ADC is designed in a 1.8 V 1P6M 0.18-mum CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19 dB and Signal to Noise and Distortion Ratio (SNDR) of 60.25 dB when a 19.02 MHz sinusoidal signal is feed-in.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; pipeline processing; power consumption; CMOS; frequency 19.02 MHz; low power consumption; pipelined analog-to-digital converter; power 13.82 mW; precharged fast power-on switched operational amplifier; signal-to-noise- and distortion ratio; sinusoidal signal; size 0.18 mum; spurious free dynamic range; voltage 1.8 V; word length 10 bit; Analog-digital conversion; Energy consumption; Nonlinear distortion; Operational amplifiers; Pipelines; Power amplifiers; Power engineering and energy; Redundancy; Sampling methods; Switches; analog-to-digital converter; pipeline; switched operational amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4244-2975-2

Electronic_ISBN

978-1-4244-2976-9

Type

conf

DOI

10.1109/ISCE.2009.5156902

Filename

5156902