Title :
A 2.5Gb/s Burst-Mode CDR based on a 1/8th rate Dual Pulse Ring Oscillator
Author :
Gierkink, Sander L J
Author_Institution :
Conexant Syst., Red Bank
Abstract :
A 2.5Gb/s burst-mode CDR uses a 1/8th rate ring oscillator with two pulses running simultaneously that are phase independent. One pulse sets the delay of the ring by phase locking it to a reference. The other pulse tracks the phase of the incoming data. Phase acquisition is instantaneous from a single data edge. Run length tolerance is greater than 72 bits. The 0.6mm2 0.13mum CMOS chip includes a CML-to-CMOS input buffer, PLL with on-chip loop filter, PRBS checker, 1:8 demux and 8 output buffers. It has 2.7UIPP jitter tolerance at 100kHz and consumes 42mW from a single 1.2V supply.
Keywords :
CMOS integrated circuits; jitter; oscillators; phase locked loops; synchronisation; CMOS chip; PLL; burst-mode CDR; dual pulse ring oscillator; jitter tolerance; on-chip loop filter; phase acquisition; phase locking; power 42 mW; run length tolerance; voltage 1.2 V; Circuits; Clocks; Delay; Frequency; Injection-locked oscillators; Jitter; Optical pulses; Passive optical networks; Phase locked loops; Ring oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405752
