Title :
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time
Author :
Kim, Moo-Young ; Shin, Dongsuk ; Chae, Hyunsoo ; Ok, Sunghwa ; Kim, Chulwoo
Author_Institution :
Korea Univ., Seoul
Abstract :
A portable multiphase clock generator, independent of input duty ratio, has been developed. The proposed open-loop and full-digital architecture has a fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is implemented to achieve high phase resolution at a wide frequency range. The generator has been implemented in a 0.18 um CMOS process and operates at variable input frequencies ranging from 800 MHz to 1.6 GHz.
Keywords :
CMOS digital integrated circuits; clocks; 2 cycle lock-time; CMOS process; Internet protocol; complementary metal-oxide-semiconductor; frequency 800 MHz to 1.6 GHz; full digital architecture; open loop all-digital clock generator; portable IP; portable multiphase clock generator; size 0.18 mum; Clocks; Delay lines; Detectors; Energy consumption; Frequency; Inverters; Phase detection; Power generation; Signal generators; Signal resolution;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405754
