A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM

Author

Khamankar, R. ; Bowen, C. ; Bu, H. ; Corum, D. ; Fujii, I. ; Gu, Y. ; Hornung, B. ; Kim, T. ; Kirkpatrick, B. ; Kirmse, K. ; Krishnan, A. ; Lin, C. ; Liu, L. ; Lowry, T. ; Montgomery, C. ; Olubuyide, O. ; Prins, S. ; Riley, D. ; Yu, S. ; Blatchford, J. ;

Author_Institution

Texas Instrum., Dallas, TX

fYear

2008

fDate

17-19 June 2008

Firstpage

176

Lastpage

177

Abstract

A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect generation from strain enhancing processes. Additionally, technology modeling has been made simpler through optimization of key processes to minimize context dependences while simultaneously providing a competitive technology. High drive currents of 1150 uA/um and 720 uA/um are obtained for nMOS and pMOS, respectively at 1.0 V and Ioff of 100 nA/mum. The first yielding SRAMs incorporating both in-situ C-doped e-SiGe and dual stress liner (DSL) in the SRAM are demonstrated.

Keywords

Ge-Si alloys; SRAM chips; carbon; integrated circuit metallisation; integrated circuit modelling; integrated circuit yield; semiconductor doping; system-on-chip; 11 level metallization; SOC application; SRAM yield; SiGe:C; dual stress liner; nMOS; pMOS; process optimization; size 45 nm; strain enhancing process; Annealing; Capacitive sensors; DSL; Etching; Implants; MOS devices; Random access memory; Space technology; Surface-mount technology; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588608

Filename

4588608