32nm device architecture optimization for critical path speed improvement

This study investigates key elements improving CMOS critical path speed. We proposed a full analysis of input signal slope impact on the switching current trajectories depending on Vt centering. Based on inverter output characteristics shape, we demonstrated that speed of low-Vt (LVT) path preferred higher drive current (I^ON) whereas high-Vt (HVT) cells speed is enhanced by lower drain induced barrier lowering (DIBL). Finally, we proposed a link with transistor architecture by optimizing halos and light-doping-drain (LDD) design to improve logic gate as a function of Vt options.