• DocumentCode
    241473
  • Title

    Operation-condition and timing-error collaborative monitoring for fixed-latency AVS designs

  • Author

    Pei-Yuan Chou ; Chung-Ling Liou ; Jinn-Shyan Wang ; Tay-Jyi Lin

  • Author_Institution
    Dept. EE, Chung-Cheng Univ., Chiayi, Taiwan
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Applying adaptive voltage scaling (AVS) to a fixed-latency design for low power is not straightforward. In this work, we propose an operation-condition and timing-error collaborative monitoring scheme to achieve this goal. The detection of operation conditions speeds up finding the most appropriate adapted-VDD, and the in-situ detection of timing errors squeezes the guard band while tolerating dynamic variations. We also use our previously proposed technique of time-borrowing with local boost so that a non-stop pipelined design can be achieved when applying the AVS for low power.
  • Keywords
    condition monitoring; low-power electronics; power aware computing; adapted-VDD; adaptive voltage scaling; dynamic variation; fixed-latency AVS design; nonstop pipelined design; operation-condition monitoring; time-borrowing; timing-error collaborative monitoring; Abstracts; Detectors; Logic gates; MOS devices; Monitoring; Temperature measurement; Temperature sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021159
  • Filename
    7021159