DocumentCode :
241476
Title :
A customized memcached FPGA chip for big data
Author :
Huiyao An ; Dunwei Liu ; Lei Li ; Ning Qi ; Tao Yu ; Peng Zhang ; Xing Zhang
Author_Institution :
Sch. of Software & Microelectron., Peking Univ., Beijing, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
With more than 80% useless applications and data wasting source in server, people use memcached as a critical solution for key-value client. But traditional memcached applications are usually realized by general Central Processing Unit (CPU), general software and Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM). There is huge potential in accelerating query speed, increasing memory capacity and reducing power consumption. We propose a particular memcached Field Programmable Gate Array (FPGA) chip solution with 13.34 million responses per second, 96GBs RAM, two 10Gbps Ethernet ports, less than 5.0us round trip latency. Gate circuit takes the place of software in memcached. Furthermore, to guarantee the correctness of network packets, this special chip supports TCP/IP protocol and memcached protocol.
Keywords :
DRAM chips; cache storage; field programmable gate arrays; transport protocols; CPU; DDR DRAM; Ethernet ports; TCP/IP protocol; central processing unit; data wasting source; double data rate synchronous dynamic random access memory; field programmable gate array chip; key-value client; memcached FPGA chip; memcached protocol; power consumption; query speed; Abstracts; Big data; Educational institutions; Field programmable gate arrays; Random access memory; Resource management; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021160
Filename :
7021160
Link To Document :
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