DocumentCode
2414768
Title
The development of a fault tolerant ULSI signal processor
Author
Stewart, A.K.J.
Author_Institution
Plessey Res. Caswell Ltd., Towcester, UK
fYear
1989
fDate
3-5 Jan 1989
Firstpage
245
Lastpage
255
Abstract
A fault-tolerant ultra large-scale integration (ULSI) signal processor which handles 32-bit floating-point data conforming to IEEE standard 754 and includes sufficient on-chip random access memory to perform a 1024-point fast Fourier transform (FFT) without reference to external memory is discussed. The chip is designed to run at 32 MHz using completely standard 1.5-μm bulk CMOS technology, with an estimated chip size of 4 cm2. In FFT mode, one FFT butterfly operation can be started every clock cycle such that a complete 1024-point complex FFT is completed in 160-μs (typ). The aim is to raise the yield of the device to the point where a multiprocessor system can be realized from a small array of these processors
Keywords
CMOS integrated circuits; VLSI; computerised signal processing; digital signal processing chips; fast Fourier transforms; 1.5 micron; 32 MHz; 32 bits; FFT butterfly operation; IEEE standard 754; bulk CMOS technology; chip size; clock cycle; fast Fourier transform; fault tolerant; floating-point data; multiprocessor system; on-chip random access memory; signal processor; yield; Bandwidth; CMOS technology; Circuit testing; Fault tolerance; Integrated circuit interconnections; Read-write memory; Signal processing; Silicon; Standards development; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47555
Filename
47555
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