Design and implementation of Dual-port Network on Chip

Compared with general Single-core systems, Multi-core systems not only have higher computing capabilities and lower power consumption but also bring high-throughput and high-parallel challenges to the communication on the chip. Depending on the design of traditional 2D-mesh Network on Chip (NoC), this paper researches a Dual-port NoC (DPN), which further enhances the parallelism of multi-core systems, such that each resource node can send or receive two-way data at the same time. Under streaming mode, this design can make every resource do binary operation to improve system´s efficiency. This paper designs and implements a 4X4 DPN on FPGA. This paper also tests throughput and flit latency of DPN and traditional 2D-mesh in different package length and sending interval. The results of tests show that throughput has increased %46.4 in average while flit latency has increased %16.5 in average.