Title :
High-K/Metal Gate Technology: A New Horizon
Author_Institution :
IBM, Hopewell Junction
Abstract :
High-K/metal gate technology represents a fundamental change in transistor structure that restarts gate length scaling, enables performance improvement and offers chip power reduction. The gate stack presented is compatible with conventional high temperature CMOS processing and existing performance enhancement elements. A new knob in the form of metal gate work function promises separate and better optimization for high performance and low power applications. This technology introduces a unique PBTI reliability mechanism for N-FET that is now well understood and modeled.
Keywords :
CMOS integrated circuits; high-k dielectric thin films; integrated circuit technology; N-FET; PBTI reliability mechanism; chip power reduction; gate length scaling; gate stack; high temperature CMOS processing; high-K/metal gate technology; metal gate work function; transistor structure; CMOS technology; Circuits; Electrostatics; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Leakage current; Stress; Technological innovation; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405765
