Thermal resistance measurements of interconnections and modeling of thermal conduction path, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack

In order to assess appropriate cooling solutions for three-dimensional (3D) chip stacks in various uses, it is important to have better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this paper, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. With regard to the thermal resistance measurements of interconnections, Yamaji et al. found it difficult to measure the thermal resistance of interconnections with the laser-flash method and pointed out that care was necessary for uniform temperature distribution in the sample when using the laser-flash method on heterogeneous specimens, such as stacked chips with interconnections. Considering this concern, we use a steady-state thermal resistance measurement method for the thermal resistance measurements of the interconnections. The thermal resistance of 200 mum-pitch-C4 (Pb97Sn3) joined samples is measured and the thermal conductivity of C4 is derived to be 18 - 24 W/mC. The secondary focus of this paper is to study the thermal resistance reduction by underfill. The effect of underfill with various interconnection pitches and diameters is obtained and also the thermal conduction path from a transistor to an interconnection is modeled.