• DocumentCode
    2414976
  • Title

    A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

  • Author

    Darabiha, Ahmad ; Carusone, Anthony Chan ; Kschischang, Frank R.

  • Author_Institution
    Toronto Univ., Toronto
  • fYear
    2007
  • fDate
    16-19 Sept. 2007
  • Firstpage
    459
  • Lastpage
    462
  • Abstract
    A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.
  • Keywords
    CMOS digital integrated circuits; decoding; parity check codes; 10GBase-T standard; CMOS; bit rate 3.3 Gbit/s; bit-serial block-interlaced min-sum LDPC decoder; decoder energy efficiency; low-density parity-check codes; power 1416 mW; routing congestion; size 0.13 μm; voltage 1.2 V; Code standards; Energy consumption; Integrated circuit interconnections; Iterative algorithms; Iterative decoding; Parity check codes; Routing; Throughput; Voltage; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-0786-6
  • Electronic_ISBN
    978-1-4244-1623-3
  • Type

    conf

  • DOI
    10.1109/CICC.2007.4405773
  • Filename
    4405773
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2414976