Title :
Towards a sub-2.5V, 100-Gb/s Serial Transceiver
Author :
Voinigescu, S.P. ; Aroca, R. ; Dickson, T.O. ; Nicolson, S.T. ; Chalvatzis, T. ; Chevalier, P. ; Garcia, P. ; Gamier, C. ; Sautreuil, B.
Author_Institution :
STMicroelectron., Crolles
Abstract :
This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.
Keywords :
BiCMOS integrated circuits; CMOS digital integrated circuits; Ge-Si alloys; data communication equipment; frequency dividers; phase locked loops; phase noise; transceivers; voltage-controlled oscillators; BiCMOS process; CMOS process; HBT static frequency dividers; SiGe; bit rate 100 Gbit/s; bit rate 87 Gbit/s; clock distribution network amplifiers; frequency 100 GHz; frequency 105 GHz; frequency 90 GHz; low-phase noise VCO; on-chip PLL; power 1.4 W; serial transceiver; size 130 nm; size 65 nm; static frequency dividers; voltage 1.2 V; voltage 2.5 V; Art; BiCMOS integrated circuits; Frequency conversion; Germanium silicon alloys; Heterojunction bipolar transistors; Phase locked loops; Production; Silicon germanium; Transceivers; Transmitters;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405776