Synthesis of Optimal On-Chip Baluns

We describe a method for synthesizing on-chip baluns. The method involves creating a scalable transformer model from electromagnetic (EM) simulations. Using this model, a quick search through the design space produces an optimal balun. The search may include constraints on insertion loss, return loss, area, etc. We used this method to design baluns for common wireless applications. The baluns were fabricated in a 90 nm RF CMOS process and measured. They were found to have good performance with insertion loss less than 1.5 dB, return loss of about 16 dB, phase imbalance of 0.25deg and amplitude imbalance of 0.25 dB. These characteristics are equal to or better than those of off-chip baluns while requiring significantly less area.