Title :
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS
Author :
Zhuang, Jingcheng ; Du, Qingjin ; Kwasniewski, Tad
Author_Institution :
Carleton Univ., Ottawa
Abstract :
A 4 GHz ADPLL-based integer-N frequency synthesizer is reported in this paper. It employs a low-complexity digital phase and frequency detector as well as a non-linear phase and frequency decision circuit to significantly reduce the hardware complexity while maintain a comparable in-lock performance to other high-complexity ADPLLs. The ADPLL was fabricated in 90 nm CMOS technology to prove its feasibility. Operating with a high-frequency-resolution DCO, the proposed low-complexity ADPLL exhibits a programmable loop bandwidth from 100 kHz to 6 MHz with and an excellent in-band phase noise performance.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; detector circuits; digital phase locked loops; frequency synthesizers; ADPLL-based integer-N frequency synthesizer; CMOS technology; bandwidth 100 kHz to 6 MHz; digital phase locked loop; frequency 4 GHz; frequency decision circuit; frequency detector; hardware complexity; in-band phase noise performance; in-lock performance; low complexity ADPLL-based frequency synthesizer; low-complexity digital phase; nonlinear phase; programmable loop bandwidth; size 90 nm; CMOS technology; Circuits; Digital filters; Frequency conversion; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405790
