Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design

At 65 nm, device and interconnect features are well below the wavelength of light used to pattern them, and shape variations significantly impact circuit characteristics. A simulation methodology to predict changes in circuit characteristics due to systematic lithography and etch effects is described and validated in silicon. A device model, which captures narrow width effects, is shown to accurately reproduce drive currents of Poly "H" structures and Active "U" structures. This model, combined with accurate lithographic contour simulation, is used to update an existing circuit netlist to give accurate delay calculations. The simulation methodology applied to various ring oscillator structures is compared to measured silicon data. In a digital IC design flow, the delay variation due to lithography and etch is calculated and used to identify and repair timing "hotspots" or parametric failures due to systematic variations.