A VLSI design with built-in SRAM arrays for implementing Full Search Block Matching Algorithm

A conventional 2-dimensional (2D) systolic processing element (PE) array of a chip used for implementing full aearch block matching algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.