Scalable fault-tolerant logic system based on regular array of locally interconnected gates

This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.