Title :
A 50MHz–812MHz, 700mW low-power PLL with a constant KVCO ring oscillator
Author :
Shunli Ma ; Jianbing Jiang ; Guangyao Zhou ; Ning Li ; Ye Fan ; Junyan Ren
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a low power phase-locked-loop (PLL) with a low variation loop bandwidth. Compared to a traditional ring oscillator based PLL, it shows a constant loop bandwidth and is insensitive to PVT variation. It is implemented by using a programmable resistor-array with multiple linear voltage-to-current (VCC) curves, which replace the traditional nonlinear one. As a result, the loop bandwidth variation is reduced and low jitter is achieved. In order to further minimize the spur of current pulse from charge pump (CP) and dividers, fully differential topology are utilized. The PLL circuits consume 0.7mA current with 1-V supply voltage in TSMC 0.13 μm process, and the lock range is from 50MHz to 812 MHz.
Keywords :
low-power electronics; phase locked loops; voltage-controlled oscillators; PVT variation insensitve; TSMC process; charge pump; constant gain VCO ring oscillator; constant loop bandwidth; current 0.7 mA; current pulse; frequency 50 MHz to 812 MHz; fully differential topology; linear voltage-current curve; low power PLL; low power phase locked loop; low variation loop bandwidth; power 700 mW; programmable resistor array; size 0.13 mum; voltage 1 V; Bandwidth; CMOS integrated circuits; Noise; Phase frequency detector; Low power; PLL system; jitter; low variation of loop bandwidth; ring oscillator;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021201
