Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance

High performance IC designs impose stringent design specifications on clock distribution networks, where clock skews must be well controlled even under the presence of environmental and process variations. As a result, clock meshes are gaining increasing popularity due to their inherent low skew and immunity to variations. While clock meshes are often analyzed in time-domain for the purpose of verification as well as tuning, the massive couplings within the passive mesh structure and in between a large number of clock drivers are challenging to handle. In contrast, frequency-domain steady-state simulation techniques such as harmonic balance (HB) are specifically advantageous since the massive passive mesh structure can be rather compactly represented using matrix transfer function matrices at a discrete set of harmonic frequencies. The remaining challenge, however, is to develop harmonic balance techniques that can efficiently simulate highly nonlinear steady-steady problems corresponding to a large number of tightly coupled clock drivers. In this paper, we present a hierarchically preconditioned algorithm that is particularly suitable to clock mesh analysis. Moreover, we show that the parallelizable nature of our algorithm allows further runtime improvement of large clock mesh analysis via parallel processing.