DocumentCode
2416029
Title
Signal Processing Architectures for Low-Noise High-Resolution CMOS Image Sensors
Author
Kawahito, S.
Author_Institution
Shizuoka Univ., Hamamatsu
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
695
Lastpage
702
Abstract
In this paper, signal processing architectures for low-noise high-resolution CMOS image sensors are reviewed and discussed. For low-noise signal readout, a column amplifier plays an important role for reducing both the noises due to a wideband output buffer and a pixel source follower. With high amplifier gain, a double-stage noise canceling technique and an advanced signal processing using oversampling techniques effectively reduce the noise due to the pixel source follower. Architectures and topologies for on-chip A/D conversion including pixel parallel, column parallel and serial schemes are also discussed. On-chip column parallel analog-to-digital (A/D) conversion is particularly important for low-noise and high-speed signal readout.
Keywords
CMOS image sensors; analogue-digital conversion; readout electronics; signal processing equipment; signal sampling; advanced signal processing; column amplifier; column parallel scheme; double-stage noise canceling; high amplifier gain; high-speed signal readout; low-noise high-resolution CMOS image sensors; low-noise signal readout; noise reduction; on-chip A/D conversion; oversampling techniques; pixel parallel scheme; serial schemes; signal processing architectures; Broadband amplifiers; CMOS image sensors; CMOS technology; Circuit noise; Diodes; Image converters; Noise cancellation; Noise reduction; Pixel; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405827
Filename
4405827
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